Most computer systems are formed of components coupled together using one or more buses, which are used to transmit information between the various system components. Present bus standards such as the Peripheral Component Interconnect (PCI) Specification, Rev. 2.1 (published Jun. 1, 1995) provide a multi-drop bus in which multiple devices are coupled to the bus. When coupled to the same bus, it is easy to read or write to devices.
However, in order to achieve higher bus interface speeds, bus architectures are moving away from multi-drop architectures and are beginning to develop point-to-point architectures. In point-to-point bus architectures, peer-to-peer communications are generally more difficult to implement due to difficulties in the synchronization, ordering and coherency of such communications. One example of a point-to-point architecture is a PCI EXPRESS® architecture in accordance with the PCI Express Base Specification, Rev. 1.0 (published Jul. 22, 2002).
Communications between serially connected devices typically involve buffering data to be sent in a transmitting device and then sending the data in a packet form to a receiving device. Various flow control schemes currently exist to control the transfer of data between the devices. One of these control schemes involves conventional credit-based flow control where initialization is accomplished by setting the transmitting device to a maximum credit level based on prior knowledge of the highest credit level supported by that device. Alternatively, in accordance with a phased-crediting HyperTransport™ approach, the transmitting device is set to the maximum credit level based on a multi-field control message transmitted from the receiving device.
In short, the initialization of these conventional credit-based flow control mechanisms consumes significant resources due to excessive overhead and restricts component compatibility based on required knowledge of credit levels between devices in communication with each other.